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Lattice Semiconductor
Correlator IP Core
Parameter Descriptions
The parameters used for con?guring the Correlator IP core are listed below. The values of these parameters must
be set prior to synthesis or functional veri?cation.
Table 1. User Con?gurable Parameters
Parameter
Parameter
Default
Parameter
Number
1
2
Parameter
DWIDTH
NUM_TAP
Description
Input data width
Number of taps
1-8
8-2048
Input Range
Input Value
4
16
Values
—
—
Minimum = 1
3
MWIDTH
Number of correlator cells
Maximum = the number of
EBR blocks in the target
4
—
LatticeEC device
4
5
6
7
8
9
10
NUM_CHAN
DTYPE
COMPLEX
OS_FACTOR
PERFORMANCE
FIFO_DEPTH
NUM_COEF_SEQ
Number of channels
Input data type
Correlation type
Oversampling rate
Performance
Input FIFO depth
Number of coef?cient
sequences
1-256
Signed, unsigned
Real, complex
1-8
1, 2, 3
1, 2, 3
1-256
2
Unsigned
Real
1
1
1
NUM_CHAN
—
“UNSIGNED”
“SIGNED”
Real = 0
Complex = 1
—
—
—
—
The basic con?guration parameters should be selected based on the type of correlation desired. These include
parameters 1, 2, 4, 5, 6, 7 and 10. The remaining parameters 3, 8 and 9 are selected based on the desired perfor-
mance of the circuit.
For parameter 3, a higher f MAX can be achieved by generating a much smaller circuit (smaller number of correlator
cells). However, for long data sequences (number of taps, or “corr_win”), this will mean that many clock cycles are
needed for each correlation result to be calculated resulting in very poor overall data throughput and long latency
times. For higher data throughput, and at the expense of a larger and therefore more complicated circuit, a higher
number of correlators should be chosen. The Correlator IP core is architected to be highly pipelined, so even for
large numbers of correlator cells, the penalty in f MAX is small; however, as the design becomes more complicated, it
will eventually reach a point where the f MAX is impacted by routing in the FPGA.
Parameter 8 should be set to 1 for the highest performance circuit. A value of 2 or 3 will result in a smaller, but sig-
ni?cantly lower performance design.
Parameter 9 sets the depth of the input FIFO. This improves throughput performance by allowing the next input
data sample to be presented to the device while the present correlation result is being calculated. However, care
must be used when changing this parameter. If the FIFO depth is set above 1, then the user must insure that a new
data sample will not be presented to the Correlator IP core for the same channel as is presently being serviced or
the new data sample will be written into the core’s internal tap memory and will corrupt the correlation which is
already in progress for that channel. If the core has been con?gured for multiple channels, and input data values for
the same channel are never presented to the core adjacent to each other in time, then the FIFO depth can be
safely increased beyond 1. For example, if the core is con?gured for eight channels, and data for each of the eight
channels is always presented in sequence, then the FIFO depth may be increased to 2 or 3. However, if the core is
con?gured for one or two channels, or the input data sequences through channels at random, then the FIFO depth
should never be increased beyond 1.
8
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